Processes for forming P-wells and N-wells on a single semiconductor substrate are well known in the art. Such P-wells and N-wells are formed to allow both N-channel and P-channel field effect transistors (FETs), respectively, to be fabricated on the same integrated circuits. In the prior art, several conventional processes have evolved, including the five process flows which are discussed next.
The first conventional process ("flow A1"), which is also known as the "blanket N-well" process, is illustrated in FIGS. 1a to 1d and described as follows:
(a) FIG. 1a shows that a thin oxide layer 111 is first formed over the entire surface of a P-type substrate 110, which is then patterned by a P-well photoresist mask 120 to allow a blanket P-type ion implantation step 130.
(b) FIG. 1b is a cross-sectional view of substrate 110 after P-well photoresist mask 120 is removed by a conventional step. FIG. 1b shows a blanket N-type ion implantation step 131, which implants N type ions through thin oxide layer 111 without using an additional photoresist masking step. Under this process, the N-type dopant is designed to have a sufficiently low concentration, so as not to counterdope the existing P-type region created by the P-type ion implantation step 130 in substrate 110 to become N-type.
(c) FIG. 1c shows a drive-in step to diffuse the implanted P-type and N-type species to form P-well 112 and N-well 113. Nitride structures 122a and 122b are then formed on oxide layer 111 to simultaneously define "island" or "active" regions of P-well 112 and N-well 113. A photoresist mask 121 is then disposed generally over N-well 113. A P-type anti-inversion ("channel-stop") implantation step 132 is then performed into P-well field regions 112a and 112b. Nitride structure 122a serves as an implantation mask for shielding P-island region 112c during the ion implantation step 132. In this process, the ion implantation steps occur prior to forming the LOCOS ("local oxidation of silicon") field oxide layer.
(d) FIG. 1d shows that photoresist mask 121 is removed, a LOCOS field oxide layer 114 is then formed, and nitride structures 122a and 122b are subsequently removed from the semiconductor surface.
A variation of flow A1, referred below as "flow A2", forms the P-wells and the N-wells, using a self-aligned N-well ion implantation step. This process, which is shown in FIGS. 2a-2d, is referred to as a "self-aligned N-well" process. The difference between flows A1 and A2 is the self-aligned N-well implantation step. Flow A2 includes the following steps:
(a) As shown in FIG. 2a, a thin oxide layer 211 is formed over the entire surface of substrate 210. A nitride layer 223 is then formed on top of thin oxide layer 211. The surface of nitride layer 223 is then patterned by a P-well photoresist mask 220 and a nitride etch. A P-type ion implantation step 230 defines a P-well region.
(b) Following the P-type ion implantation step 230, P-well photoresist mask 220 is removed and a LOCOS oxide layer 214 is formed, as shown in FIG. 2b. The remaining nitride layer 223 is then removed. An N-type blanket self-aligned implantation step 231 defines an N-well region, with LOCOS oxide layer 214 protecting the P-well region defined in the steps of FIG. 2a above.
(c) As shown in FIG. 2c, a drive-in step drives the implanted P-type and N-type species into substrate 210, thereby forming P-well 212 and N-well 213, respectively. LOCOS oxide layer 214 is then removed, and nitride structures 222a and 222b are formed over thin oxide layer 211 to define the island regions of P-well 212 and N-well 213, respectively. A photoresist mask 224 is then formed above N-well 213. An ion implantation step 232 then provides the channel-stop ion implantation into field regions 212a and 212b.
(d) Finally, as shown in FIG. 2d, photoresist mask 224 is removed, and a LOCOS field oxide layer 215 is formed. Nitride structures 222a and 222b are then removed.
A third conventional method, known as the "the blanket P-well process" and referred below as "flow B"), is shown in FIGS. 3a-3d. The process of flow B provides the P-well and the N-well structures in a manner similar to flow A1, except N-well ion implantation step 331 uses a photoresist mask 325 to define the N-well region. In flow A1, the corresponding step to N-well ion implantation step 331 is ion implantation step 130 (FIG. 1a), which defines the N-well region. Consequently, the subsequent P-type implantation step 330 is a blanket ion implantation step self-aligned to an N-well. Thus, the process steps in flow B are:
(a) FIG. 3a shows that a thin oxide layer 311 is first formed over the entire surface of a P-type substrate 310, which is then patterned by a N-well photoresist mask 325 to allow a blanket N-type ion implantation step 331.
(b) FIG. 3b is a cross-sectional view of substrate 310 after N-well photoresist mask 325 is removed by a conventional step. FIG. 3b shows a blanket P-type ion implantation step 330, which implants P-type ions through thin oxide layer 311 without using a photoresist masking step. Under this process, the P-type dopant is implanted to a sufficiently low concentration, so as not to counterdope the existing N-type regions created by N-type ion implantation step 331 in substrate 310 to become P-type.
(c) FIG. 3c shows a drive-in step to drive the implanted P-type and N-type species to form P-well 312 and N-well 313. Nitride structures 322a and 322b are then formed on thin oxide layer 311 to simultaneously define island regions of P-well 312 and N-well 313. A photoresist mask 321 is provided above N-well 313. A P-type channel stop implantation step 332 introduces P-type species into P-well field regions 312a and 312b. Nitride structure 322a serves as an implantation mask for shielding P-island region 312c during the ion implantation step 332. In this process, the ion implantation steps occur prior to forming the LOCOS ("local oxidation of silicon") field oxide layer.
(d) FIG. 3d shows that photoresist mask 321 is removed, a LOCOS field oxide layer 314 is then formed, and nitride structures 322a and 322b are removed from the semiconductor surface.
A fourth method, known as "the retrograded P-well process" and referred below as "flow C", is similar to flow B, except that, after the LOCOS field oxide layer is formed, an implantation masking step is used to adjust P-well doping levels for the active regions and the field regions. Flow C, which combines P-well and field implantation steps, is described as follows in conjunction with FIGS. 4a-4d:
(a) FIG. 4a shows a thin oxide layer 411 formed over the entire surface of substrate 410. An N-well photoresist mask 425 is then patterned over oxide layer 411, and an N-type ion implantation step 431 defines an N-well region.
(b) As shown in FIG. 4b, photoresist mask 425 is removed after the N-type ion implantation step 431. A drive-in step drives the implant N-type species into substrate 410 to form N-well 413. Nitride structures 422a and 422b are then formed over thin oxide layer 411 to define the P-type and N-type island regions, respectively.
(c) As shown in FIG. 4c, a LOCOS field oxide layer 414 is then formed. Nitride structures 422a and 422b are then removed, and a photoresist mask 421 is then provided over N-well 413. A P-type ion implantation step 432 and a subsequent drive-in step provide P-well 412. Dopant concentration in field regions 412a and 412b can be controlled by a channel stop ion implantation step, using an additional masking step (FIG. 4d).
In the processes described above, field regions of the N-well can also be formed using similar steps to those discussed above with respect to fields region of the P-well.
A fifth prior art method, which is referred below as "flow D", is shown in FIGS. 5a-5d. Flow D is similar to both flow A and flow B, except that the island regions in the P-wells and the N-wells are defined separately for N-channel and the P-channel transistors, so that the P-well field regions can be defined without an additional photoresist mask. Flow D is described as follows:
(a) As shown in FIG. 5a, a P-well 512 and an N-well 513 are formed using conventional photoresist masks, P-type and N-type ion implantation and subsequent drive-in steps. Thereafter, a thin oxide layer 511 is formed over the entire surface of substrate 510. A nitride layer 523 is then formed over thin oxide layer 511.
(b) As shown in FIG. 5b, N-well field regions 512a and 513b are then formed using a photoresist mask 525, a nitride etch (forming structures 523a and 523b), and an N-type ion implantation step 531 performed through the exposed regions of oxide layer 511.
(c) As shown in FIG. 5c, photoresist mask 525 is removed, and a photoresist mask 526 is then patterned over the semiconductor surface to protect N-well 513 and to define an island region for P-well 512. Nitride layer 523c is then formed by etching the exposed regions of nitride layer 523a. A P-type ion implantation step 532 defines P-well field regions 512a and 512b.
(d) Finally, as shown in FIG. 5d, photoresist mask 526 is then removed. LOCOS field oxide layer 514 is then formed. Nitride structures 523b and 523b are then removed.
All the above described prior art process flows share a significant disadvantage in that the formation of P-wells and N-wells is accomplished by one or two ion implantation steps followed by a subsequent lengthy thermal or drive-in step, thereby resulting in a costly and time-consuming process. For example, to provide a deep well profile necessary to prevent the "latch-up" phenomenon, e.g. a well depth of 2 microns, drive-in periods can exceed 24 hours. In addition, because entire well bodies, i.e., both field and island regions, are formed at the same time, island regions cannot be independently optimized for desirable device and isolation characteristics. The island regions in the P- and N-wells cannot be individually optimized because the optimum dopant concentration in the island regions are too low for adequate isolation. Field regions in the P- and N-wells, however, are doped three or four times the dopant concentrations in the island regions. The above-described conventional processes each also require an extra photoresist masking step for forming optical alignment targets (OATs), which are structures formed on the semiconductor surface to allow proper alignment between the various photoresist masking steps.
Accordingly, there is a need for an efficient method for fabricating P-wells and N-wells which optimizes transistor performance and creates OATs without increasing the number of photoresist masking steps.